Design & Verification Engineer (Will work in Japan)ID:20841
16,000,000 VND ~ 47,000,000 VNDDist 33个月以上前概述
薪资
16,000,000 VND ~ 47,000,000 VND
产业类别
Software
工作内容
- Work with Design Engineers in verification and validation of circuit designs.
- Develop design standards and guidelines to ensure quality and performance.
- Perform layout, logical, design, feasibility, and electrical verification of circuit components.
- Participate in design reviews and recommend improvements.
- Perform failure analysis and suggest corrective actions.
- Work with management to coordinate and execute projects within allotted timelines and budget.
- Determine technology requirements, dependencies and deliverables based on project specifications.
- Prepare design verification plan based on design specifications.
- Plan and schedule assigned projects for timely completion.
- Utilize latest techniques, tools and technologies for design verification activities.
- Maintain design verification environment and track and close design bugs.
- Develop design verification methodologies and implement standard debug flows.
资格
应征条件
<Must>
- English for internal communication
- Experience as Design & Verification Engineer : At least 2 years
- Verilog language or SystemC/C/C++
<Advantage>
- SystemVerilog language, Synopsys/Cadence
- Design skill priority, Verilog, SystemVerilog, SVA, UVM Methodology, C, SystemC英文
Intermediate Level
其他语言
None
附加信息
福利制度
- Bonus 【3 times / per year】
- Transportation allowance
- Social insurance
- Health check
- Salary raise工作时间
8:30 ~ 17:30
假日
Sat, Sun, Holiday
职业类别
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