Design & Verification Engineer (Will work in Japan)ID:20841
16,000,000 VND ~ 47,000,000 VNDDist 3Over 3 months agoOverview
Salary
16,000,000 VND ~ 47,000,000 VND
Industry
Software
Job Description
- Work with Design Engineers in verification and validation of circuit designs.
- Develop design standards and guidelines to ensure quality and performance.
- Perform layout, logical, design, feasibility, and electrical verification of circuit components.
- Participate in design reviews and recommend improvements.
- Perform failure analysis and suggest corrective actions.
- Work with management to coordinate and execute projects within allotted timelines and budget.
- Determine technology requirements, dependencies and deliverables based on project specifications.
- Prepare design verification plan based on design specifications.
- Plan and schedule assigned projects for timely completion.
- Utilize latest techniques, tools and technologies for design verification activities.
- Maintain design verification environment and track and close design bugs.
- Develop design verification methodologies and implement standard debug flows.
Qualifications
Requirement
<Must>
- English for internal communication
- Experience as Design & Verification Engineer : At least 2 years
- Verilog language or SystemC/C/C++
<Advantage>
- SystemVerilog language, Synopsys/Cadence
- Design skill priority, Verilog, SystemVerilog, SVA, UVM Methodology, C, SystemCEnglish Level
Intermediate Level
Other Language
None
Additional Information
Benefit
- Bonus 【3 times / per year】
- Transportation allowance
- Social insurance
- Health check
- Salary raiseWorking Hour
8:30 ~ 17:30
Holiday
Sat, Sun, Holiday
Job Function
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