Design & Verification Engineer Member (Have Sign On Bonus! Full remote!)ID:18664
20,000,000 VND ~ 53,000,000 VNDDist 33ヶ月以上前概要
給与
20,000,000 VND ~ 53,000,000 VND
業界
Software
仕事内容
- Work with Design Engineers in verification and validation of circuit designs.
- Develop design standards and guidelines to ensure quality and performance.
- Perform layout, logical, design, feasibility, and electrical verification of circuit components.
- Participate in design reviews and recommend improvements.
- Perform failure analysis and suggest corrective actions.
- Work with management to coordinate and execute projects within allotted timelines and budget.
- Determine technology requirements, dependencies and deliverables based on project specifications.
- Prepare design verification plan based on design specifications.
- Plan and schedule assigned projects for timely completion.
- Utilize latest techniques, tools and technologies for design verification activities.
- Maintain design verification environment and track and close design bugs.
- Develop design verification methodologies and implement standard debug flows.
求めている人材
応募条件
<Must>
- English for internal communication
- Experience of semiconductor field : 3 years above
- Verilog language
<Advantage>
- SystemVerilog language, Synopsys/Cadence
- Design skill priority, Verilog, SystemVerilog, SVA, UVM Methodology, C, SystemC英語
Intermediate Level
その他言語
None
その他
福利厚生
- Bonus 【3 times / per year】
- Transportation allowance
- Social insurance
- Health check
- Salary raise
- Full remote
- Sign on Bonus就業時間
8:30 ~ 17:30
休日
Sat, Sun, Holiday
職種
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